Data processing systems can include various components that interact with each other to process an instruction. One component may be a memory management unit (MMU) that can manage retrieval of data and/or instructions from a physical memory upon a transaction request by one or more processor threads of a processing unit. Some data processing systems use virtual addresses to improve retrieval efficiency. For example, a thread may generate a transaction request that includes a virtual address for data or instruction and supply the virtual address to the MMU. The MMU can translate the virtual address to its corresponding physical address to access the data in physical memory. In some MMUs, a look-up table maps a virtual address to a physical address, such as in a translation lookaside buffer (TLB).
The transaction request can be routed to the resource that includes pages corresponding to the physical address via an interface, also known as a channel, such as a bus. Data processing systems can include different interfaces for accessing different system resources. A buffer, such as a first in first out (FIFO), can manage the physical addresses and determine the interface to which to provide each physical address for accessing a resource. For example, a buffer can be coupled to a TLB to receive the physical addresses and provide them to an address decoder that identifies the interface on which to provide each physical address to access a resource.
The interfaces are coupled to the resources. Each interface may have different characteristics, such as speed or bandwidth, for routing physical addresses of the transaction requests. Differing characteristics may cause physical addresses to back-up in the buffer and delay processing even if new transaction requests for different resources are provided by the TLB. For example, a physical address to access a first interface may fill the buffer because the first interface is being used to access a resource. Physical addresses for routing on other interfaces or the first interface may be backed-up because the buffer is full. Furthermore, the address decoder is activated for every access using a physical address to one of the interfaces, consuming power with each access.
Accordingly, a memory management unit system and process is desirable that can route physical addresses to interfaces and decrease processing delays, decrease power consumption, and/or provide better quality service to a processor.